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/* CLKPR - Clock Prescale Register */
#define CLKPS0 0 // Clock Prescaler Select Bit 0
#define CLKPS1 1 // Clock Prescaler Select Bit 1
#define CLKPS2 2 // Clock Prescaler Select Bit 2
#define CLKPS3 3 // Clock Prescaler Select Bit 3
#define CLKPCE 7 // Clock Prescaler Change Enable

// Crystal Oscillator division factor: 2
#pragma optsize-
CLKPR=(1<<CLKPCE);
CLKPR=(0<<CLKPCE) | (0<<CLKPS3) | (0<<CLKPS2) | (0<<CLKPS1) | (1<<CLKPS0);
#ifdef _OPTIMIZE_SIZE_
#pragma optsize+
#endif

/* ***** USART0 *********************** */
/* UDR0 - USART I/O Data Register */
#define UDR0_0 0 // USART I/O Data Register bit 0
#define UDR0_1 1 // USART I/O Data Register bit 1
#define UDR0_2 2 // USART I/O Data Register bit 2
#define UDR0_3 3 // USART I/O Data Register bit 3
#define UDR0_4 4 // USART I/O Data Register bit 4
#define UDR0_5 5 // USART I/O Data Register bit 5
#define UDR0_6 6 // USART I/O Data Register bit 6
#define UDR0_7 7 // USART I/O Data Register bit 7

/* UCSR0A - USART Control and Status Register A */
#define MPCM0 0 // Multi-processor Communication Mode
#define U2X0 1 // Double the USART transmission speed
#define UPE0 2 // Parity Error
#define DOR0 3 // Data overRun
#define FE0 4 // Framing Error
#define UDRE0 5 // USART Data Register Empty
#define TXC0 6 // USART Transmitt Complete
#define RXC0 7 // USART Receive Complete

/* UCSR0B - USART Control and Status Register B */
#define TXB80 0 // Transmit Data Bit 8
#define RXB80 1 // Receive Data Bit 8
#define UCSZ02 2 // Character Size
#define TXEN0 3 // Transmitter Enable
#define RXEN0 4 // Receiver Enable
#define UDRIE0 5 // USART Data register Empty Interrupt Enable
#define TXCIE0 6 // TX Complete Interrupt Enable
#define RXCIE0 7 // RX Complete Interrupt Enable

/* UCSR0C - USART Control and Status Register C */
#define UCPOL0 0 // Clock Polarity
#define UCSZ00 1 // Character Size
#define UCPHA0 UCSZ00 // For compatibility
#define UCSZ01 2 // Character Size
#define UDORD0 UCSZ01 // For compatibility
#define USBS0 3 // Stop Bit Select
#define UPM00 4 // Parity Mode Bit 0
#define UPM01 5 // Parity Mode Bit 1
#define UMSEL00 6 // USART Mode Select
#define UMSEL0 UMSEL00 // For compatibility
#define UMSEL01 7 // USART Mode Select
#define UMSEL1 UMSEL01 // For compatibility

/* UBRR0H - USART Baud Rate Register High Byte */
#define UBRR8 0 // USART Baud Rate Register bit 8
#define UBRR9 1 // USART Baud Rate Register bit 9
#define UBRR10 2 // USART Baud Rate Register bit 10
#define UBRR11 3 // USART Baud Rate Register bit 11

/* UBRR0L - USART Baud Rate Register Low Byte */
#define UBRR0 0 // USART Baud Rate Register bit 0
#define UBRR1 1 // USART Baud Rate Register bit 1
#define UBRR2 2 // USART Baud Rate Register bit 2
#define UBRR3 3 // USART Baud Rate Register bit 3
#define UBRR4 4 // USART Baud Rate Register bit 4
#define UBRR5 5 // USART Baud Rate Register bit 5
#define UBRR6 6 // USART Baud Rate Register bit 6
#define UBRR7 7 // USART Baud Rate Register bit 7

// USART initialization
// Communication Parameters: 8 Data, 1 Stop, No Parity
// USART Receiver: On
// USART Transmitter: On
// USART0 Mode: Asynchronous
// USART Baud Rate: 9600
UCSR0A=(0<<RXC0) | (0<<TXC0) | (0<<UDRE0) | (0<<FE0) | (0<<DOR0) | (0<<UPE0) | (0<<U2X0) | (0<<MPCM0);
UCSR0B=(1<<RXCIE0) | (0<<TXCIE0) | (0<<UDRIE0) | (1<<RXEN0) | (1<<TXEN0) | (0<<UCSZ02) | (0<<RXB80) | (0<<TXB80);
UCSR0C=(0<<UMSEL01) | (0<<UMSEL00) | (0<<UPM01) | (0<<UPM00) | (0<<USBS0) | (1<<UCSZ01) | (1<<UCSZ00) | (0<<UCPOL0);
UBRR0H=0x00;
UBRR0L=0x33;